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| AT83C5103 - AT87C5103 PPAP AT83C5103 / AT87C5103 C51 LPC 8-Bit Microcontroller ATMEL P/N : AT8xC5103xxx-IBRAL PPAP Submission Date: Supplier: Address: March 2003 ATMEL-NANTES SA La Chantrerie BP 70602 44306 NANTES Cedex 3 France Tel : 33(0) 2 40 18 18 18 Fax : 33(0) 2 40 18 19 20 Rev. 1 : Initial Submission - 2003 March 1 AT83C5103 - AT87C5103 PPAP Table of Contents TABLE OF CONTENTS.............................................................................................................................................................2 REVISION HISTORY.................................................................................................................................................................4 PPAP CHECKLIST .....................................................................................................................................................................5 1 DESIGN RECORDS ...........................................................................................................................................................6 1.1 1.2 2 PRODUCT SPECIFICATION ...........................................................................................................................................6 PACKAGE OUTLINE........................................................................................................................................................6 ENGINEERING CHANGE DOCUMENTS .....................................................................................................................6 2.1 CDC CERTIFICATE OF DESIGN, CONSTRUCTION AND QUALIFICATION ...................................................................6 2.1.1 General Product Information ...................................................................................................................................6 2.1.2 Process Technology Information..............................................................................................................................7 2.2 PRODUCT DESIGN ........................................................................................................................................................8 2.2.1 Product Design Information.....................................................................................................................................8 2.2.2 Package Technology Information.............................................................................................................................8 2.2.3 Packing Delivery Information ..................................................................................................................................9 2.2.4 Final Test Information..............................................................................................................................................9 2.2.5 Device Cross Section..............................................................................................................................................10 2.3 QUALIFICATION AND CHANGE PROCEDURE.............................................................................................................11 2.3.1 Qualification methodology .....................................................................................................................................11 2.3.2 Change Procedure..................................................................................................................................................12 2.3.3 Qualification test methods......................................................................................................................................13 3 4 5 ENGINEERING APPROVAL .........................................................................................................................................14 DESIGN FMEA .................................................................................................................................................................14 PROCESS FLOW DIAGRAMS ......................................................................................................................................14 5.1 5.2 5.3 FRONTEND..................................................................................................................................................................14 ASSEMBLY ..................................................................................................................................................................15 TEST AND PACKING .....................................................................................................................................................15 6 7 8 PROCESS FMEA ..............................................................................................................................................................15 DIMENTIONAL RESULTS ............................................................................................................................................16 PERFORMANCE TEST RESULTS ...............................................................................................................................16 8.1 QUALIFICATION RESULTS .........................................................................................................................................16 8.1.1 Wafer Process Qualification ..................................................................................................................................16 8.1.2 Package Qualification ............................................................................................................................................16 8.1.2.1 8.1.2.2 8.1.2.3 8.1.2.4 8.1.2.5 8.1.2.6 Product Qualification .......................................................................................................................................................17 Device Reliability ............................................................................................................................................................17 Package Reliability ..........................................................................................................................................................17 Electrical Distribution in Operating Life-Test .................................................................................................................18 Failure Mechanisms and Corrective Actions ...................................................................................................................18 ESD Results (HBM) - MIL-STD 883E method 3015.7 ...................................................................................................18 2 Rev. 1 : Initial Submission - 2003 March AT83C5103 - AT87C5103 PPAP 8.1.2.7 Latchup Results................................................................................................................................................................18 8.2 PRODUCT CHARACTERIZATION ................................................................................................................................18 8.2.1 Characterization environment................................................................................................................................18 8.2.2 Corner lot's splits ...................................................................................................................................................18 8.2.3 Results / Parameter capability ...............................................................................................................................19 8.2.3.1 8.2.3.2 8.2.3.3 8.2.3.4 8.2.3.5 Input Voltages..................................................................................................................................................................19 Output Voltages ...............................................................................................................................................................20 Input currents ...................................................................................................................................................................21 Pull-Down Resistor on Reset Pin.....................................................................................................................................22 Consumptions ..................................................................................................................................................................22 9 INITIAL PROCESS STUDY............................................................................................................................................23 9.1 9.2 SCMOS3 PROCESS (Z92G) .......................................................................................................................................23 SCMOS3NV PROCESS (Z94X)..................................................................................................................................24 MEASUREMENT SYSTEM ANALYSIS STUDY ....................................................................................................25 QUALIFIED LABORATORY DOCUMENTATION ...............................................................................................25 CONTROL PLAN.........................................................................................................................................................25 PART SUBMISSION WARRANT..............................................................................................................................26 APPEARANCE APPROVAL REPORT.....................................................................................................................27 BULK MATERIAL REQUIREMENTS.....................................................................................................................27 SAMPLE PRODUCTION PARTS ..............................................................................................................................27 MASTER SAMPLE ......................................................................................................................................................27 CHECKING AIDS ........................................................................................................................................................27 CUSTOMER-SPECIFIC REQUIREMENTS ............................................................................................................27 10 11 12 13 14 15 16 17 18 19 Rev. 1 : Initial Submission - 2003 March 3 AT83C5103 - AT87C5103 PPAP Revision history Rev 0 1 Issue January 2003 March 2003 Modification Notice Initial version Update after product characterization completion (3V and 5V ranges) Applicable from Rev. 1 : Initial Submission - 2003 March 4 AT83C5103 - AT87C5103 PPAP PPAP Checklist Requirements Table of contents PPAP Checklist 1. Design Records 2. Engineering Change Documents 3. Engineering Approval 4. Design FMEA 5. Process Flow Diagrams 6. Process FMEA 7. Dimensional Results 8. Records of Material / Performance Test Results 8.1 Material Test Records 8.2 Performance Test Records 9. Initial Process Study 10. Measurement System Analysis Study 11. Qualified Laboratory Documentation 12. Control Plan 13. Part Submission Warrant (PSW) 14. Appearance Approval Report 15. Bulk Material Requirements Checklist 16. Sample Production Parts 17. Master Sample 18. Checking Aids 19. Customer Specific Requirements Included yes yes yes yes yes Project Risk analysis yes yes Not Applicable Not applicable to IC yes yes yes yes yes yes Not applicable to IC Not applicable to IC Separate order Not attached Not Applicable Not defined Rev. 1 : Initial Submission - 2003 March 5 AT83C5103 - AT87C5103 PPAP 1 Design Records 1.1 Product Specification Please see ATMEL's Data Sheet AT83C5103 / AT87C5103 Low-Pin-Count 8-Bit Microcontroller http://www.atmel.com/ 1.2 Package Outline See attached file : SSOP16_outline.pdf 2 Engineering Change Documents 2.1 CDC Certificate of Design, Construction and Qualification 2.1.1 General Product Information Product Name: Function: Wafer Process: Package Type : Locations: Process Development, Product Development Wafer Plant QC Responsibility Probe Test Assembly Final Test Lot Release Shipment Control Quality Assurance Reliability Testing Failure Analysis ATMEL Nantes , France ATMEL Nantes , France ATMEL Nantes , France ATMEL Nantes, France ATMEL Nantes , France AMKOR Philippines TSTI Philippines ATMEL Nantes, France Global Logistic Center, Philippines ATMEL Nantes, France ATMEL Nantes, France ATMEL Nantes, France AT87C5103: 16k EPROM AT83C5103: 16k ROM 8 Bits Microcontroller, 16Kbytes memory CMOS 0.5um SSOP 16 Rev. 1 : Initial Submission - 2003 March 6 AT83C5103 - AT87C5103 PPAP 2.1.2 Process Technology Information Process Type (Name): Base Material: Wafer Thickness (final) Wafer Diameter Number Of Masks Gate Oxide (Logic transistors) Material Thickness Gate Oxide (EPROM cell) Material Thickness Polysilicon Number of Layers Thickness Poly 1 Thickness Poly 2 Metal Number of Layers Material: Layer 1 Thickness Layer 2 Thickness Layer 3 Thickness Passivation Material Thickness 3 AlCu 5150A 5150A 7650A Z94: SiO2 / Oxynitride Z92: SiO2 / Nitride Z94: 3000A / 15000A Z92: 2600A / 6400A Z94 (SCMOS3 Non Volatile - EPROM) Z92 (SCMOS3 - ROM) Epi (Z94) Bulk (Z92) 475m 150 mm Z94: 22 Z92: 14 Silicon Dioxide 110 A Silicon Dioxide 110 A Z94:2 Z92:1 2000A 3000A Rev. 1 : Initial Submission - 2003 March 7 AT83C5103 - AT87C5103 PPAP 2.2 Product Design 2.2.1 Product Design Information Die Size Pad Size Opening Logic Effective Channel Length Gate Poly Width (min.) Gate Poly Spacing (min.) Metal 1 Width Metal 1 Spacing Metal 2 Width Metal 2 Spacing Metal 3 Width Metal 3 Spacing Contact size Via 1 size Via 2 size 3500m * 3090m (10.82mm2) 80m * 80m 0.5mm 0.50mm 0.60mm 0.60mm 0.70mm 0.80mm 0.70mm 0.80mm 0.70mm 0.60m 0.60m 0.60m 2.2.2 Package Technology Information Package weight Chip separation method Lead frame Material Thickness Lead plating Die attach Material Type Wire bonding Material Diameter Method Molding Material Flammability rating Marking Method 0.14 g Sawing Cu 6 mils Electroplated Sn/Pb 85/15 Silver epoxy Ablestick 84-1 LMISR4 Au 1.0 mil Thermosonic MP8000AN UL94V-0 Top : Printed ink Back : Laser 8 Rev. 1 : Initial Submission - 2003 March AT83C5103 - AT87C5103 PPAP 2.2.3 Packing Delivery Information Dry packing Tube packed Primary Material Number per unit Secondary Material Number per unit Labelling (minimum) Bar coding Reel packed Primary Material Carrier tape Cover tape Number per unit Secondary Number per unit Labelling (minimum) 2.2.4 Final Test Information Probe equipment Probe temperature Test equipment Test temperature Maverick GT or PT 125o C Maverick GT or PT - 40o C + 125o C + 25o C No Tube Antistatic PVC 77 Box Cardboard 385 Device type, quantity, Date code, Production code Code 39 to EIA-556-A Reel Conductive black polystyrene Antistatic film 2000 Box 1 Device type, quantity, Date code, Production code Rev. 1 : Initial Submission - 2003 March 9 AT83C5103 - AT87C5103 PPAP 2.2.5 Device Cross Section Rev. 1 : Initial Submission - 2003 March 10 AT83C5103 - AT87C5103 PPAP 2.3 Qualification and Change Procedure 2.3.1 Qualification methodology All product qualifications are split into three distinct steps as shown below. Before a product is released for use, successful qualification testing are required at wafer, device and package level. Wafer Level Reliability consists in testing individually basic process modules regarding their well known potential limitations (Electromigration, Hot Carriers Injection, Oxide Breakdown, NVM Data Retention). Each test is performed using wafer process specific structures. Device reliability is covering either dice design and processing aspects. The tests are performed on device under qualification, but generic data may also be considered for reliability calculation. For each package type proposed in the Datasheet, it is verified that qualification data are available. If not qualification tests are carried out for the new package types. In addition, one package type is selected to verify packaging reliability of the device under qualification. - Product Qualification W afer Level Device (Design / Process) Packaging Reliability Reliability Reliability Rev. 1 : Initial Submission - 2003 March 11 AT83C5103 - AT87C5103 PPAP 2.3.2 Change Procedure All changes are controlled by ECN (Engineering Change Notice). All major changes are notified to the customers using products that are affected by the change. A major change is defined as a change which affects the electrical and/or mechanical specification as defined in the datasheet or which affects the following parameters as defined hereafter: 1 1-1 1-2 1-3 1-4 1-5 1-6 2 2-1 2-2 2-3 2-4 2-5 3 3-1 3-2 3-3 3-4 3-5 4 4-1 4-2 4-2 4-3 General Major Changes Manufacturing line Sequence of fabrication process cycle Material type Electrical parameter External physical dimension Die size Changes specific to wafer fabrication area Doping method Gate oxide formation method Equipment change Layer Thickness Module dimensions Changes specific to assembly process area Sawing method Die attach Wire interconnect tools Molding process Tinning method Changes specific to test area Specification limit Test coverage reduction Product identification Final conditioning Rev. 1 : Initial Submission - 2003 March 12 AT83C5103 - AT87C5103 PPAP 2.3.3 Qualification test methods General Requirements for Plastic packaged CMOS Ics. Standard MIL-STD 883 Method 1005 MIL-STD 883 Method 1005 MIL-STD 883 Method 3015.7 JEDEC 78 AEC Q100 Method 005 AEC Q100 Method 005 MIL-STD 883 Method 1010 Atmel PAQA0184 EIA JESD22-A101 EIA JESD22-A110 EIA JEDEC 20-STD MIL-STD 883 Method 2003 MIL-STD 883 Method 2015 Test Description Electrical Life Test (Early Failure Rate) 48 hours 140C Electrical Life Test (Latent Failure Rate) 1000 hours 140C Dynamic or Static Electrostatic Discharge HBM +/-2000v 1.5kOhm/100pF/3 pulses Latch up 50mW power injection, 50% overvoltage @125C NVM Endurance Program Erase Cycles 25C NVM Data Retention High Temperature Storage 165C Temperature Cycling 1000 cycles -65C/150C air/air HAST after Preconditioning 144 hours 130C/85%RH 85/85 Humidity Test 1000 hours 85C/85%RH HAST 336 hours 130C/85%RH/5.5V Preconditioning Soldering Stress 220C/235c/3 times Solderability Marking Permanency Acceptance 0/300 - 48h 0/100 - 500h 0/3 per level 0/5 per stress 0/50 - 100kc 0/50 - 500h 0/50 - 500c 0/50 - 72h 0/50 - 500h 0/50 - 168h 0/11 per class 0/3 0/5 Rev. 1 : Initial Submission - 2003 March 13 AT83C5103 - AT87C5103 PPAP 3 Engineering Approval AT8xC5103 is qualified since January 2003 Released to production is planned on February 2003 Release to Production loop approval is the following : O O O O O O O O O O Head of Technical Center Technical Project Leader Project Manager Product Engineering Operation Backend Operation Frontend Quality Management Marketing Business Planning Test Development 4 Design FMEA For new products, a Project Risk Analysis is performed during Feasibility phase under the Project Leader responsibility, using expertise in many areas including Design. This Project Risk Analysis and related Action Plan to reduce the risks are reviewed at each milestone of the project. The Project Risk Analysis report is an ATMEL internal document . 5 Process Flow Diagrams 5.1 Frontend 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Incoming inspection of silicon wafers. PBL (Z94) or Locos (Z92) Isolation. Non Volatile Well Implants (Z94). MOS N-Well implants (Z94 & Z92) and N Well diffusion. (Z92) EPROM floating Gate oxidation and Poly deposition (Z94). EPROM ONO stack oxidation (Z94). HVMOS gate oxidation (Z94) MOS P-Well Implants (Z94 & Z92). Depleted MOS Well Implants (Z94). MOS definition (Z94). MOS Gate oxidation (Z94 & Z92). Polysilicon deposition and MOS gate definition(Z94 & Z92). EPROM control gate definition (Z94) and EPROM Implants (Z94). 14 Rev. 1 : Initial Submission - 2003 March AT83C5103 - AT87C5103 PPAP 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. MOS / HVMOS Implants with Spacer definition. (Z94 & Z92) Silicide Hard mask definition.(Z94 & Z92) Salicide module. (Z94 & Z92) ILD deposition and SOG planarization (Z94 & Z92) Contact etching and Plug1 filling. (Z94 & Z92) Metal 1 deposition and etching (Z94 & Z92) IMD1 and REB planarization (Z94 & Z92) Via1 etching and Plug2 filling (Z94 & Z92) Metal 2 deposition and etching (Z94 & Z92) IMD2 and REB planarization (Z94 & Z92) Via2 etching and Plug3 filling (Z94 & Z92) Metal 3 deposition and etching (Z94 & Z92) Passivation deposition and etching (Z94 & Z92) UV erasing (Z94) Test site (Z94 & Z92) Wafer sort1 (Z94 & Z92) Bake (Z94) Wafer sort2 (Z94) 5.2 Assembly Referenced Process Flow Chart : Amkor Philippines P470-0501-0204 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. Wafer mount Wafer saw First optical Die bonding Wire bonding Molding Solder plating Top marking Trim and form Final visual inspection 5.3 1. 2. 3. 4. 5. 6. 7. Test and Packing Room temperature initial test Burn-in Room temperature test Hot test Cold test Final quality checks Packing 6 Process FMEA Process FMEA for 0.5uM Z92 and Z94 are implemented and are only shown upon request during customer audits. Rev. 1 : Initial Submission - 2003 March 15 AT83C5103 - AT87C5103 PPAP 7 Dimentional Results Only necessary for new packages and/or new assembly locations/lines Not necessary for this PPAP, because parts are produced in standard SSOP16 package Package dimensions were checked during Package Qualification (see chapter 8.1.2 for more details) 8 Performance Test Results 8.1 Qualification Results 8.1.1 Wafer Process Qualification ATMEL 0.5m SCMOS3 wafer process is qualified since 1997, september ATMEL 0.5m SCMOS3NV wafer process is qualified since 2000, february 8.1.2 Package Qualification Performed on product G1001 at AMKOR Philippines : QTP 0329 (11/10/1996) The following table summarizes the SSOP16 package qualification results Test Description Humidity 85C/85RH Thermal Cycles - 65C/100C Lead Finish Adhesion Construction Analysis Marking Permanency IR Reflow mounting Physical Dimentions IR Reflow mounting Step 1000H 1000C Result 0/45 0/45 0/3 0/5 0/5 0/45 0/5 0/45 Comment AC96009 With preconditionning Without preconditionning 168H 168H Conclusions : No failure was observed during the reliability tests. The qualification of SSOP16L at AMKOR Philippines is pronounced. Rev. 1 : Initial Submission - 2003 March 16 AT83C5103 - AT87C5103 PPAP 8.1.2.1 Product Qualification 8.1.2.2 Device Reliability The test results are summarized in the table below: Lot Z42859B Device Type AT83C5103 Test Description EFR Dynamic Life Test LFR Life Test Z40807C TSS463 EFR Dynamic Life Test LFR Life Test Z27921A TS83C51RX2 EFR Dynamic Life Test LFR Life Test Z27300A TS83C51RC2 ESD HBM LATCH-UP Power Injection Over-voltage Step 12h 500h 1000h 12h 500h 1000h 12h 500h 1000h 4000v 50mw 10v Result 0/800 0/77 0/77 1/776 0/77 0/77 0/297 0/100 0/100 0/3 0/5 0/5 Comment overstress Class 3 of MIL STD 883 Method 3015 Latch-up free (up to 120mW) 8.1.2.3 Package Reliability In this section are presented the packaging qualification measurements done on AT83C5103 in SSOP16 . Lots Z42859B Device Type AT83C5103 Test Description 85/85 Humidity Thermal Cycles Step 500h 1000h 500c 1000c 96h 500h 1000h Csam Elect Result Comment 0/77 0/77 0/77 0/5 0/5 0/72 0/77 0/77 0/77 0/11 0/231 After preconditioning level1 After preconditioning level1 Ball shear cpk:1.22 (30 pads) Wire pull cpk:1.39 (30 wires) HAST after Soldering Stress High Temperature Storage 165C Moisture sensitivity JESD20 - level1 Rev. 1 : Initial Submission - 2003 March 17 AT83C5103 - AT87C5103 PPAP 8.1.2.4 Electrical Distribution in Operating Life-Test Not available 8.1.2.5 Failure Mechanisms and Corrective Actions Not applicable 8.1.2.6 ESD Results (HBM) - MIL-STD 883E method 3015.7 Product 87C5103 is classified in class 1 of the MIL-STD Product 83C5103 is classified in class 3 of the MIL-STD 8.1.2.7 Latchup Results Power Injection Over-voltage 50mw 10v 0/5 0/5 Latch-up free (up to 120mW) 8.2 Product Characterization 8.2.1 Characterization environment Tester: Corner lot: Process: ROM Code: Assy package: Maverick 2 / ntomv23 Z42859 Z92G - Bulk 3ZAA 3Z (PDIL24.300) 8.2.2 Corner lot's splits In order to characterize the product with realistic excursion of the process, corner run splits have been manufactured using : O O Variation onsLeffP and LeffN Variations on VTP and VTN Rev. 1 : Initial Submission - 2003 March 18 AT83C5103 - AT87C5103 PPAP 8.2.3 Results / Parameter capability 8.2.3.1 Input Voltages Symbol Parameter Specification 1.89V max Input High Level exept RST & XTAL1 2.31V max 2.52V max 3.15V max 3.85V max 1.89V max 2.31V max VIH1 Input High Level RST 2.52V max 3.15V max 3.85V max 1.89V max 2.31V max VIH1 Input High Level XTAL1 2.52V max 3.15V max 3.85V max 0.44V min 0.56V min VIL Input Low Level 0.62V min 0.8V min 1.0V min Vcc 2 .7V 3 .3V 3.6V 4.5V 5.5V 2.7V 3.3V 3.6V 4.5V 5.5V 2.7V 3.3V 3.6V 4.5V 5.5V 2.7V 3.3V 3.6V 4.5V 5.5V Temp Average -40C 1.22V 130C 1.09V -40C 1.42V 130C 1.29V -40C 1.5V 130C 1.39 -40C 1.77V 130C 1.68V -40C 2.04V 130C 2.03V -40C 0.99V 130C 0.86V -40C 1.13V 130C 0.96V -40C 1.2V 130C 1.02V -40C 1.41V 130C 1.22V -40C 1.64V 130C 1.44V -40C 1.41V 130C 1.45V -40C 1.75V 130C 1.79V -40C 1.93V 130C 1.97V -40C 2.45V 130C 2.5V -40C 3.06V 130C 3.1V -40C 1.19V 130C 1.06V 1.39V -40C 130C 1.25V 1.48V -40C 130C 1.35V -40C 1.75V 130C 1.62V -40C 2.03V 130C 1.92V Cpk 4.2 5.7 4.5 5.6 5.0 5.7 6.8 6.2 7.2 7.1 6.1 4.7 8.0 8.4 9.5 11 .1 11.4 12.8 13.5 19.5 8.0 6.5 7.0 6.8 6.8 6.7 6.4 6.5 6.2 6.0 3.2 3.7 3.0 3.1 3.1 2.9 2.9 2.3 2.1 1.8 Conditions VIH Rev. 1 : Initial Submission - 2003 March 19 AT83C5103 - AT87C5103 PPAP 8.2.3.2 Output Voltages Symbol Parameter Specification 2.2V min Output High Level in VOH_PP Push-Pull Mode Ports 1 & 4 4.0V min 1.7V min 3.5V min Output High Level in Pseudo Bidirectional Mode Ports 1 & 4 4.2V min 3.8V min 3.0V min 2.4V min 0.3V max 0.45V max VOL Output Low Level Ports 1 & 4 1.0V max 0.3V max 2.7V 1.0V max 4.5V 2.7V 4.5V Vcc 2.7V 4.5V 2.7V 4.5V Temp -40C 130C -40C 130C -40C 130C -40C 130C -40C 130C -40C 130C -40C 130C -40C 130C -40C 130C -40C 130C -40C 130C -40C 130C -40C 130C Average 2.7V 2.7V 4.5V 4.5V 2.35V 2.06V 4.27V 4.13V 4.41V 4.35V 4.25V 4.08V 4.0V 3.6V 2.57V 2.48V 0.05V 0.08V 0.35V 0.35V 0.72V 0.70V 0.05V 0.08V 0.37V 0.39V Cpk 163 112 138 106 9.3 2.5 29 15 14.1 9.9 15 7.3 15.6 5.9 9.2 3 11.4 5.8 2.2 1.9 3.3 3.8 11.4 5.7 13.5 10.8 Conditions IOH = 0.1 mA IOH = 1mA IOH = 10mA IOH = 30mA IOH = 60mA IOH = 10mA IOH = 0.1mA IOH = 1.6mA IOH = 3.5mA IOH = 0.1mA IOH = 1.6mA VOH Rev. 1 : Initial Submission - 2003 March 20 AT83C5103 - AT87C5103 PPAP 8.2.3.3 Input currents Symbol Parameter Input Low current in Pseudo Bidirectional Mode Input Transition current in Pseudo Bidirectional Mode Specification Vcc 3.3V -50mA 3.6V 5.5V 3.3V -650mA 3.6V 5.5V 3.3V Input Leakage current in Input Mode 3.6V 5.5V 10mA 3.3V 3.6V 5.5V 3.3V Input Leakage current in Open Drain Mode 3.6V 5.5V 10mA 3.3V 3.6V 5.5V Temp Average -40C -7mA 130C -4mA -40C -8.3mA 130C -4.9mA -40C -19.7mA 130C -11.8mA -40C -94.1mA 130C -56.1mA -40C -119.4mA 130C -71.6mA -40C -301.5mA 130C -189.8mA -40C 0.7nA 130C 2.7nA -40C 1.6nA 130C 3.5nA -40C 1.1nA 130C 4.1nA -40C 56nA 130C 78.4nA -40C 61.6nA 130C 68.6nA -40C 92nA 130C 48.2nA -40C 0.1nA 130C 3nA -40C 1.1nA 130C 3nA -40C 0.8nA 130C 2.9nA -40C 55.8nA 130C 81nA -40C 63nA 130C 88.2nA -40C 92.2nA 130C 150.6nA Cpk 26.2 56.4 22.2 48 8.8 21.6 32.8 67.9 25.2 52.6 7.6 17.8 188.5 120.9 184.7 118.6 186.3 123 107.5 52.6 106.6 48.2 75.4 27.5 181.9 121.7 180.8 119.4 182.7 125.2 106.9 50.3 101 47.5 71.5 27.4 Conditions IIL Vin = 0.45V ITL VIN = 2V VIN = 0V ILI_Z VIN = VCC VIN = 0V ILI_OD VIN = VCC Rev. 1 : Initial Submission - 2003 March 21 AT83C5103 - AT87C5103 PPAP 8.2.3.4 Pull-Down Resistor on Reset Pin Symbol Parameter Specification Vcc 2.7V Min = 30Kohms RPDRST Pull-Down Reset Resistor Max = 150Kohms (Rom version only) 3.3V 3.6V 4.5V 5.5V Temp -40C 130C -40C 130C -40C 130C -40C 130C -40C 130C Average 39.4K 67.7K 39.7K 68.1K 39.8K 68.3K 40.2K 68.9K 40.7K 69.5K Cpk 4.8 7.1 4.8 7 5 6.9 5.1 6.7 5.2 6.5 Conditions 8.2.3.5 Consumptions Symbol IPD Parameter Power-Down current Specification 50mA max 100mA max 14.2mA max 3.6V 21.5mA max 10.8mA max 3.6V 18.2mA max 5.5V 5.5V 3.3V Idle Mode ICCIDL consumption Vcc 3.3V 3.6V 5.5V 3.3V ICCOP Operating consumption Temp 130C -40C 130C -40C 130C -40C 130C -40C 130C -40C 130C -40C 130C Average 8mA 9mA 16mA 7.9mA 6.8mA 8.9mA 7.7mA 15.2mA 13.9mA 5.5mA 4.8mA 6.2mA 5.4mA 11.4mA 9.9mA Cpk 2.7 1.8 2.2 7.5 6.9 6.3 5.7 5.8 5.1 5.9 7.7 4.6 6.2 4.8 6.0 Conditions See datasheet 16.7Mhz CPU running 16.7Mhz Cpu inactive Rev. 1 : Initial Submission - 2003 March 22 AT83C5103 - AT87C5103 PPAP 9 Initial Process Study 9.1 SCMOS3 process (Z92G) Parameters controlled during Electrical Test : NMOS/PMOS :junction Breakdown Voltage, Threshold voltage, electrical width & length, Thin oxide Breakdown Voltage, Sub-threshold current. Sheet Resistance : N+, P+, WELL, PolyN, PolyP, Unsalicided Poly Metal continuity / isolation: metal1, metal2, metal3 Contacts/ Vias1 & Vias2 resistance Contacts Breakdown Voltage Salicide isolation Cpk history (Last update 23/01/2003) Z92G Cpk distribution 120% 100% 80% Repartition (%) 60% 40% 20% 0% Cpk<1.33 (%) Cpk>=1.33 & <1.66 (%) Cpk>=1.66 (%) 02/01 5% 5% 89% 02/02 3% 5% 92% 02/03 5% 3% 92% 02/04 8% 5% 86% 02/05 5% 19% 76% 02/06 5% 5% 89% 02/07 8% 11% 81% Mois 02/08 0% 3% 97% 02/09 8% 5% 86% 02/10 14% 0% 86% 02/11 0% 3% 97% 02/12 3% 5% 92% 03/01 3% 3% 95% Cpk<1.33 (%) Cpk>=1.33 & <1.66 (%) Cpk>=1.66 (%) Lineaire (Cpk<1.33 (%)) Lineaire (Cpk>=1.66 (%)) Rev. 1 : Initial Submission - 2003 March 23 AT83C5103 - AT87C5103 PPAP 9.2 SCMOS3NV process (Z94X) Parameters controlled during Electrical Test : Same as Z92G with EPROM junction Breakdown voltage, Programmed threshold voltage, ONO breakdown voltage High Voltage MOS: oxide breakdown voltage, High voltage threshold voltage, High voltage junction breakdown Depleted MOS: threshold voltage. Cpk history (Last update 23/01/2003) Z94X Cpk distribution 120% 100% 80% Distribution (%) 60% 40% 20% 0% Cpk<1.33 (%) Cpk>=1.33 & <1.66 (%) Cpk>=1.66 (%) 02/01 0% 5% 95% 02/02 22% 4% 73% 02/03 7% 2% 91% 02/04 9% 2% 89% 02/05 4% 2% 93% 02/06 7% 2% 91% 02/07 4% 7% 89% Mois 02/08 4% 4% 91% 02/09 16% 0% 84% 02/10 4% 4% 91% 02/11 13% 9% 78% 02/12 4% 0% 96% 03/01 4% 0% 96% Cpk<1.33 (%) Cpk>=1.33 & <1.66 (%) Cpk>=1.66 (%) Lineaire (Cpk<1.33 (%)) Lineaire (Cpk>=1.66 (%)) Rev. 1 : Initial Submission - 2003 March 24 AT83C5103 - AT87C5103 PPAP 10 Measurement System Analysis Study Repeatability and Reproductability tests are performed on all the manufacturing equipments. Critical parameters are followed by Cpk but equipment performance is followed by GRR and maintenance follow-up. 11 Qualified Laboratory Documentation Internal Lab - COMPLIANT QS-9000 3rd edition Application Lab Calibration Lab Characterization Lab Chemical Lab Environmental Lab Technology Analysis Lab Scope Check the functionality of products to customer applications Standard Gage Calibration Product and process characterization before completing industrialization Incoming inspection on chemical products and process monitoring on DI water , gases Reliability Tests Failure Analysis and Yield enhancement 12 Control Plan See attached file : Control Plan for Z92G process Rev. 1 : Initial Submission - 2003 March 25 AT83C5103 - AT87C5103 PPAP 13 Part Submission Warrant Rev. 1 : Initial Submission - 2003 March 26 AT83C5103 - AT87C5103 PPAP 14 Appearance Approval Report Not Applicable for IC 15 Bulk Material Requirements Not Applicable for IC 16 Sample Production Parts Not attached, delivered previously 17 Master Sample Not attached. 18 Checking Aids Not applicable 19 Customer-Specific Requirements Not specified. Rev. 1 : Initial Submission - 2003 March 27 |
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